Power semiconductor devices, such as bipolar power semiconductors, for example diodes, thyristors, gate turn-off thyristors (GTOs) and gate controlled thyristors (GCTs), may be produced from silicon wafers. After a production step in which the silicon wafers were subject to different processes, such as an implantation process, a diffusion process, a photolithographic process and a metallization process, the silicon wafers are formed such as cut to circular discs, and a first or upper bevel and a second or lower bevel are ground on the high-voltage blocking p/n-junction(s). These bevels usually require a protection by means of an electric passivation.
Issues of passivation often represent and thus act against fatal defects such as unstable device operation caused by changes in film properties, instability, water permeability, permeability of movable ions such as sodium, pinholes and cracks, and aluminium metal disconnection or corrosion due to degradation and stress. This is for example described in the Toshiba Semiconductor Reliability Handbook, 2011 and shows the importance of respective passivating coatings.
For example, with regard to BiMOS chips, a typical passivation stack for high voltage BiMOS semiconductor devices may firstly be based on a material layer adapted to saturate dangling bonds and to drain trapped charges. A respective coating may for example be formed from semi-insulating polycrystalline silicon (SIPOS) doped amorphous silicon (α-Si), and silicon nitride (SiN). Secondly typical passivations are based on an ion barrier material layer which may be silicon nitride (Si3N4) and thirdly on a layer of polyimide as mechanical protection. SIPOS is typically deposited by LPCVD using a mixture of SiH4 and N2O with a N2 carrier at a temperature of 625° C. followed by annealing at 900° C. for 30 minutes. A typical sheet resistance for SIPOS is in the order of 1E12 Ohm/Sq.
With regard to bipolar discretes, one of the known passivation materials is amorphous hydrogenated carbon (a-C:H, also known as diamond-like carbon, DLC) which can be deposited in a PECVD process inside a parallel plate plasma reactor.
Regarding devices based on silicon carbide (SiC), an important design feature for passivating coatings of such devices is to find a passivation that can provide a defect-free interface to the silicon carbide base material. Approaches are made by SiO2 and Si3N4 materials. For low voltage designs, there are typically no charge drainage layers. David W. Tong et al., “Interface effects of SIPOS passivation”, IEEE transactions on Electron Devices, Vol. 33, 1986, describes the effects of passivating silicon wafers with semi-insulating polycrystalline silicon (SIPOS).
Document U.S. Pat. No. 8,541,317 B2 describes a method for applying a double-sided deposition of amorphous hydrogenated carbon as a-C:H-layers onto a silicon wafer. The wafer includes a first main side having a first bevel on a border of the first main side, and a second main side having a central area and a second bevel on a border of the second main side surrounding the central area. The method includes simultaneously exposing the first and second bevels to a plasma in order to create the deposition, wherein amorphous hydrogenated carbon is applied as the plasma.
Document EP 0 751 574 A2 further describes a compression-type power semiconductor device and particular a high-blocking voltage bipolar power semiconductor device. The end surface of the power semiconductor device is shaped into a positive bevel so as to relieve the electric field intensity. The silicon end surface is covered with a passivation rubber of silicone rubber.
Document U.S. Pat. No. 5,831,291 describes a semiconductor device comprising a plurality of IGBT-like cells arranged in groups on a single wafer of silicon. This document describes that a double bevel with negative bevel and positive bevel followed by etching of the bevelled surfaces and application of a dielectric coating of silastomer or resin, may be used. Alternative profiles, e.g. a double positive bevel, may be employed.
G. Mitic et al., “IGBT module technology with high partial discharge resistance”, Proceedings of the 36th IAS meeting, Chicago, 2001, vol. 3 pp. 1899-1904, describe IGBT modules which have a coating made of a layer of doped amorphous silicon, i.e. a-Si:H, or further of amorphous germanium (a-Ge:H) or amorphous carbon (a-C:H) at the ceramic material of the substrates.
Document EP 2 337 070 A1 further describes an electronic device which comprises a substrate, a metal layer formed on the substrate and a field grading means located along an edge of the metal layer The field grading means has a non-linear electrical resistivity and is located on the substrate along at least one edge formed between the at least one metal layer and the insulating substrate. The filed grading means may comprise a matrix with a filer, such as a microvaristor filler, such as ZnO.
Document U.S. Pat. No. 3,628,106 describes a semiconductor device having a semiconductor crystal associated with a junction passivant in a manner to improve the electrical properties of the semiconductor device and the mechanical properties of the passivated semiconductor crystal. In detail, glass passivant layers are associated with upper and lower curved edges to protect respective junctions.
The before-described materials for coating regions of junction terminations of the power semiconductor devices, or the wafers, respectively still have room for improvements.
New coating materials are known, such coating materials, however, are used for totally different purposes which cannot be compared to coating of bevelled regions and in fact are solely used for mechanical protection.
Document US 2015/0001700 A1 describes a power module comprising a baseplate and a substrate, the substrate being an isolation material having opposing metallized sides, for example being a DBC substrate. A die is attached to the metallized top side of the substrate and the top side metallization is connected to one or more terminals by electrical connections. It is further described that a parylene coating is applied to the module. In fact, after having formed the whole module structure, the coating is applied and thus coats the corrosion-sensitive components within the module, such as the dies, the electrical connections and the metallized top side of the substrate. Therefore, parylene is not used for coating junction terminations comprising p/n-junctions.
Document US 2008/0173988 A1 describes a method for producing semiconductor chips. According to this method, especially the backside of the chips, i.e. the side which will be directed towards a substrate, is coated with Parylene. Again, parylene is not used for coating junction terminations comprising p/n-junctions.
Document US 2009/0045511 A1 describes an integrated circuit. The integrated circuit includes a substrate including a contact pad, a redistribution line coupled to the contact pad, and a dielectric material layer between the substrate and the redistribution line. The integrated circuit includes a solder ball coupled to the redistribution line and a parylene material layer sealing the dielectric material layer and the redistribution line. Again, parylene is not used for coating junction terminations comprising p/n-junctions.
In Document U.S. Pat. No. 4,126,931 and also in U.S. Pat. No. 3,684,592 a power semiconductor device is disclosed comprising a substrate having a first side and a second side, whereby the first side and the second side being located opposite to each other.
There is still room for improvements especially regarding producing power semiconductor modules and especially regarding providing a passivating coating on junction terminations having p/n-junctions, or junction terminations, respectively especially with regard to an electrical passivation.